1. Field of the Invention
The present invention generally related to a layout pattern data correction method, a method for manufacturing a semiconductor device and a program storage medium readable by a computer. More particularly, the invention relates to a layout pattern data correction apparatus, a method for manufacturing a semiconductor device and a program storage medium readable by a computer suitable for improving dimension accuracy of a semiconductor device by means of inhibiting pattern distortions stemming from such pattern forming processes as optical lithography and etching.
2. Description of the Background Art
The proceedings for manufacturing a semiconductor device generally includes pattern forming processes such as optical lithography and etching. Where circuit patterns are to be photoengraved by optical lithography, so-called optical proximity effect, i.e., a phenomenon in which optical interference causes errors to pattern shapes becomes more pronounced the closer the width or pitch of circuit patterns to the wavelength of light for optical exposure. Dimensional changes that can occur in the etching process become greater the higher the density differences among the patterns in question. That is, the changes become more distinct as the patterns grow finer and the circuit pattern spacing becomes narrower.
The problem of dimensional changes stemming from pattern miniaturization is difficult to be resolved solely by improvements in the wafer process. Instead, the problem is generally dealt with by correcting layout patterns. Layout patterns are corrected conventionally by one of two methods. One method involves simulating the pattern forming processes and using the results of the simulation as the basis for correcting the patterns. The other method is so-called rule-based pattern correction whereby the patterns are corrected according to predetermined rules.
The simulation-based layout pattern correction method promises highly accurate correction. As a disadvantage, the method requires a tremendous amount of processing time, which renders it less practical than the rule-based pattern correction method. On the other hand, the rule-based pattern correction method has no need for complex calculations and thus has the advantage of effecting high-speed processing. As a disadvantage, the latter method has difficulty in correcting layout patterns with high accuracy.
How rule-based pattern correction is carried out conventionally will now be described with reference to FIGS. 15 through 19.
FIG. 15 is a schematic view of design layout patterns of metal wiring in a semiconductor device. The design layout patterns of FIG. 15 include one thick-line pattern 10 and four thin-line patterns 12 through 18. The thin-line patterns 14 through 18 are located close to the thick-line pattern 10, and the thin-line pattern 12 is positioned slightly away from the thick-line pattern 10.
Where the design layout patterns of FIG. 15 are to be formed by semiconductor processes, pattern distortions attributable to optical lithography and etching are likely to occur particularly on the edges of the thin-line patterns 12 through 18. To implement the design layout patterns with accuracy requires suitably correcting the edges of the thin-line patterns 12 through 18.
FIG. 16 is a schematic view showing correction target edges 20 through 27 which are extracted as edges to be subjected to correction while mask drawing data for optical lithography are being prepared. As shown in FIG. 16, the correction target edges 20 through 27 corresponds to the edges of the thin-line patterns 12 through 18. In conventional rule-based pattern correction, the target edges 20 through 27 are corrected so as to offset pattern distortions when the mask is drafted.
FIG. 17 is a schematic view of a correction pattern 28 having a correction target edge 24 as a center axis. The correction pattern 28 is formed by expanding the correction target edge 24 vertically and horizontally by an amount L. In the conventional rule-based pattern correction setup, the correction pattern of FIG. 17 is created for each of all extracted correction target edges 20 through 27.
FIG. 18 is a schematic view of corrected layout patterns. In the process of preparing the mask drawing data, these corrected layout patterns are obtained by adding a correction pattern 20 to the design layout patterns, i.e., by OR'ing the design layout patterns and the correction pattern 20. In conventional rule-based pattern correction, an optical lithography-ready mask is prepared on the basis of the corrected layout patterns shown in FIG. 18.
As described, the conventional rule-based pattern correction method using relatively simple steps is capable of preparing a mask that takes into account the adverse effects of pattern distortions stemming from optical lithography and etching. When thus prepared, the mask is used to transcribe the corrected layout patterns onto a semiconductor wafer. After etching and other related processes, metal wiring patterns are formed on the semiconductor wafer with the effects of pattern distortions minimized.
The optical proximity effect in optical lithography and the loading effect in etching vary with pattern density. Where patterns are minuscule and circuits are highly integrated, changes of these effects are particularly pronounced. Thus if layout patterns are high in density due to intensive circuit miniaturization, uneven pattern distortions is likely to occcur depending on the pattern density.
FIG. 19 is a schematic plan view of metal wiring formed by conventional rule-based pattern correction techniques. As mentioned, the conventional rule-based pattern correction involves uniformly correcting all edges 20 through 27 that have been extracted as target edges to be corrected. It follows that if densely arranged metal wiring is formed by the techniques above, some of the correction target edges are bound to be corrected excessively. Consequently, the metal wiring partially develops distorted portions 30 through 34 as shown in FIG. 19. As described, the conventional rule-based pattern correction method is plagued by the difficulty in implementing highly precise correction of layout patterns as the patterns become finer and the circuits integrated in higher degrees than before.